For electronic devices from toys to spacecraft
By Jack Smith
For 40-plus years, hobbyists and engineers have used the 555 timer in electronic devices from toys to spacecraft. Hans R. Camenzind designed this integrated circuit (IC) in 1970 when working at Signetics. He was experimenting with ways to synthesize tuned circuits on an IC chip without using inductors. Signetics brought it to market in 1971. Within a year, both National Semiconductor and Fairchild Semiconductor were producing it as well. Now, at least 15 semiconductor manufacturers offer the 555 timer.
Signetics, which was later acquired by Philips, introduced the 555 timer as the SE555, which is the metal can version; and the NE555, which is the plastic dual inline package (DIP). National Semiconductor’s designation is LM555; Texas Instruments offers SE555, NA555, SA555, and the TLC555, which is the low-power CMOS version.
Modes and characteristics
The highly stable 555 timer can generate accurate time delays or oscillation. The design provides means for triggering and resetting the device. In the time-delay mode, an external resistor and capacitor precisely control the time. For oscillator operation, two external resistors and one capacitor accurately control the free-running frequency and duty cycle. Falling waveforms can trigger and reset the circuit. The output circuit can source or sink up to 200 mA or drive transistor-transistor logic (TTL) circuits.
The 555 timer has three main modes: bistable, monostable, and astable. “Bistable” signifies two stable states—high and low. In the bistable mode, the 555 acts like a Schmitt trigger. A Schmitt trigger produces an output when the input exceeds a specified level. The output continues until the input falls below a specified level. With the 555, a trigger at one input sets the output to high; a trigger at another input sets the output to low. The output retains its value until the input changes sufficiently to trigger a state change.
In the monostable mode, the 555 is effectively a “one-shot” because the circuit produces one pulse of a set length in response to a trigger input. The trigger can come from a pushbutton, relay contact closure, or from another circuit. The output of a circuit configured in monostable mode stays low until it is triggered.
In the astable mode, the 555 becomes an oscillator producing a continuous stream of pulses at frequencies up to 2 MHz. The output continually switches between the high and low states, producing a square wave. An astable circuit has no stable state, thus the name “astable.”
The 555 timer’s operation
The 555 timer’s trigger level is about 1/3 of VCC, which is the supply voltage. Its threshold level is about 2/3 of VCC. These levels can be altered using the Control Voltage terminal (Pin 5). When the Trigger input (Pin 2) falls below the trigger level, the internal flip-flop is set and the Output (Pin 3) goes high. If the Trigger input is above the trigger level and the Threshold input is above the threshold level, the flip-flop is reset and the Output is low. The Reset input (Pin 4) can override all other inputs and can be used to initiate a new timing cycle. If Pin 4 is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the Discharge terminal (Pin 7) and Ground (Pin 1). All unused inputs should be tied to an appropriate logic level to prevent false triggering (see “The 555 Timer Connections” sidebar).
Figure 1. Basic bistable circuit configuration using a 555 timer.
Let’s dig deeper into the 555 timer’s three major operating modes by discussing their operation. When using a 555 timer in bistable mode, there’s no need to use equations to determine component values. The bistable circuit has no associated time constants. The simple schematic in Figure 1 shows two resistors R1 and R2 connected between VCC and the Trigger and Reset inputs. These resistors hold the Trigger and Reset inputs high until pushing either the Trigger or Reset pushbutton grounds one or the other of these inputs.
Figure 2. Waveforms associated with the 555 timer in bistable mode.
As shown in Figure 2, pushing the Trigger pushbutton grounds Pin 2, effectively making the Trigger input of the 555 timer low, which drives the Output high. Pushing the Reset pushbutton grounds Pin 4, making the Reset input low. This drives the Output low. The Control and Discharge inputs are not used.
Bistable circuits are also known as flip-flops because they flip to one state when triggered, then flop back to the other state when reset. Bistable circuits can be used in switching and latching circuits, counters, shift registers, and primitive memory circuits. They can also be used in relay control circuits.
Figure 3. Basic monostable circuit configuration using a 555 timer.
In the monostable mode, a transistor inside the timer keeps the external capacitor C in a discharged state (Figure 3). Applying a negative-going trigger pulse to Pin 2 sets the internal flip-flop, which releases the virtual short-circuit across capacitor C and drives the Output at Pin 3 high. The voltage across capacitor C increases exponentially for a period of t = 1.1RAC. Another way to say this is the capacitor charges to 2/3 of the VCC level. The equation provides a means to calculate the period and to select the timing by manipulating resistor and capacitor values.
Figure 4. Waveforms associated with the 555 timer in monostable mode.
When the voltage across capacitor C reaches 2/3 of the VCC level, the 555’s internal comparator resets the internal flip-flop, which in turn discharges capacitor C and drives the Output low. The internal comparator’s charge and threshold levels are directly proportional to the supply voltage. This means that the timing interval is independent of supply voltage. Figure 4 shows the waveforms associated with the 555 timer’s monostable mode.
Figure 5. This graph indicates capacitor and resistor values for monostable circuit timing. Note that the graph is based on a log-log scale.
Top Trace: Input, 5 V/Div.
Middle Trace: Output, 5 V/Div.
Bottom Trace: Capacitor voltage, 2 V/Div.
Time = 0.1 ms/Div.
VCC = 5 V
RA = 9.1 kO
C = 0.01 µF
If a trigger pulse is applied during the timing cycle when the output is high, it won’t affect the circuit as long as the Trigger input returns to a high state at least 10μs before the end of the timing interval. The trigger should be driven high before the end of timing cycle. However, applying a negative pulse to the Reset terminal resets the circuit. The Output then remains low until the next trigger pulse. To avoid the possibility of false triggering, connect the Reset terminal to VCC when not using the reset function. Use the graph in Figure 5 to easily determine capacitor and resistor values for various monostable circuit timing.
Adjusting the length of the timing cycle can turn the basic monostable circuit into a frequency divider. Divide-by circuits are used in frequency synthesis, counting, multiplexing, and many other logic and switching applications that require period- or frequency-dividing functions.
Figure 6. A monostable-connected 555 timer becomes a PWM circuit when a continuous pulse train is applied to Pin 2 and a modulation signal is applied to Pin 5.
The 555 timer connected in monostable mode can also be configured as a pulse-width modulation (PWM) circuit. Applying a continuous pulse train to the Trigger terminal and a modulation signal such as a sine wave to the Control Voltage terminal (as shown in Figure 6) results in a PWM signal at the Output.
Figure 7. Basic astable circuit configuration using a 555 timer.
In the astable mode, the Trigger and Threshold terminals are connected together so that it continually triggers itself as a free-running multivibrator (Figure 7). The external capacitor C charges through RA + RB and discharges through RB. The ratio of RA and RB precisely sets the duty cycle, which can be determined by:
D = RB/(RA + 2RB)
The capacitor C charges and discharges between 1/3 of VCC and 2/3 of VCC. Output of the astable circuit is high during the charge time, which is determined by:
t1 = 0.693(RA + RB)C
The Output is low during the discharge time, which is determined by:
t2 = 0.693(RB)C
The total period is T = t1 + t2 = 0.693(RA + 2RB)C.
The astable circuit’s frequency of oscillation is F = 1/T = 1.44/(RA + 2RB)C.
Figure 8. Waveforms associated with the 555 timer in astable mode.
Figure 9. This graph indicates capacitor and resistor values for astable circuit operation at different free-running frequencies. Note that the graph is based on a log-log scale.
As in the triggered mode, the charge and discharge times, and therefore the frequency, are independent of the supply voltage. Figure 8 shows the waveforms associated with the 555 timer’s astable mode of operation. Use the graph in Figure 9 to easily determine capacitor and resistor values for various free-running frequencies.
If variable frequencies are desired, substitute a series resistor-potentiometer combination for RA. The fixed resistor connects to VCC and to one leg of the potentiometer. The other leg of the potentiometer connects to the Discharge terminal and resistor RB. The potentiometer wiper connects to either one of the end connections, depending on the relationship desired between potentiometer rotation direction and frequency change. The added series resistance between VCC and the potentiometer keeps the full VCC from being applied directly to the Discharge terminal when the potentiometer is at 0Ω.
Top Trace: Output, 5 V/Div.
Bottom Trace: Capacitor voltage, 1 V/Div.
Time = 20 µs/Div.
VCC = 5V
RA = 3.9kO
RB = 3kO
C = 0.01 µF